This invention relates generally to digital multipliers, and more particularly to high-speed, large scale integrated circuit multipliers for digital signal processing and general data processing applications.
Digital multipliers are one of the basic building blocks in digital signal and data processing systems. The conventional multiplier architectures that are in common use are generally very similar. A typical multiplier architecture has 2.sup.n -bit parallel inputs for an X operand and 2.sup.n -bit parallel inputs for a Y operand. These inputs are clocked into the multiplier through separate registers under control of clock enable circuitry. A full clock cycle is required to input the X and Y operands.
Conventional multiplication techniques use a modified Booth recoding scheme to generate partial products for the operands by pairs of bits, rather than single bits at a time. A Wallace tree configuration adder, with carry/save adders, is conventionally used to add up the partial products. A carry/lookahead adder is commonly used for adding the final products. The product is a binary number of 2.sup.n+1 parallel bits, which is commonly truncated or rounded to 2.sup.n bits for output.
In large (e.g., 16.times.16 bit) general purpose multipliers, that may be used for signed fractional arithmetic, this product may be input as an intermediate product to a format adjusting shifter. In conventional practice, this shifter is designed to left-shift the most significant 2.sup.n bits to align a binary point in the product with a binary point in one of the operands. The left shift truncates the highest order bit, which represents the -1.0.times.-1.0 product of +1.0 in two's complement binary arithmetic. It also produces an empty bit location between the most significant bits and the least significant 2.sup.n bits. In conventional practice, it is customary to replicate the sign bit in this empty bit location.
The final product is output to an output register, which is controlled by clock enable circuitry similar to that of the input registers. Commercially-available multipliers have 2.sup.n output lines and all output the most significant 2.sup.n bits of the product. If the least significant 2.sup.n bits of the product are to be output, these are multiplexed onto the output lines or onto input lines of one of the operands. To output a product of the 2.sup.n most significant bits from the output registers requires a second full clock cycle and to output an entire product of 2.sup.n+1 bits requires two full clock cycles.
Typically, conventional multipliers incorporate a rounding feature. If rounding is used, the user cannot tell with certainty whether the correct product is zero.
The foregoing and other characteristics of conventional multiplier architectures turn out to be limiting and cumbersome to systems designers seeking to incorporate conventional multipliers in signal processing or data processing systems.